In general, a memory device is divided into a p-type transistor and an n-type transistor. Further, memory devices usually comprise poles, commonly referred to as: a source region, a drain region, a gate electrode, and a substrate.
Among the four poles, the substrate includes a structure that is commonly called a well. Wells are generally characterized by a lower concentration of impurities than that of the source and drain regions, e.g., by about 1/10000 or 1/100000. In addition, substrates generally have two types of wells, namely, an n-type well and a p-type well.
Wells are located in a well-region. Within the well region, a well pickup region is formed to stabilize the potential of the well region.
FIG. 1 illustrates a conventional semiconductor device, having a substrate 100 and a well region 105. Well region 105 further comprises a first drain region 102a, a source region 103, and a second drain region 102b; a first gate electrode 101a positioned between the first drain region 102a and the source region 103; a second gate electrode 101b positioned between the second drain region 102b and the source region 103. First gate electrode 101a and second gate electrode 101b are connected via a gate electrode connector 101c. Well region 105 also typically comprises a well pickup region 104.
The first and second gate electrodes 101a and 101b, the source region 103, the first and second drain regions 102a and 102b, and the well pickup region 104 are electrically connected to external wiring lines (not shown), respectively, through contact metals 111, 113, 112a, 112b, and 114.
In the conventional semiconductor device, the well pickup region 104 is formed at the edge of the substrate 100, which results in an increase of the size of the device.